Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies

Azam, T., Cheng, B., Roy, S. and Cumming, D.R.S. (2010) Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies. Electronics Letters, 46(4), pp. 273-274. (doi: 10.1049/el.2010.2817)

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An asymmetric 6T-SRAM cell design is presented for reliable lowpower circuit operation under large variability. A low overhead write assist circuit is added to increase the write-noise-margin (WNM) and improve the write speed/power. Sizing is used to strengthen the pull-down transistor of the feedback inverter of the single ended read circuit to enhance the static-noise-margin (SNM). Monte Carlo simulations indicate a 90% improvement in SNM and a boost in the WNM of 108% compared to the conventional 6T-SRAM design. Comparative analysis of a 65nm 64 x 32 bit SRAM designed using both SRAM cells (Symmetric-6T and Asymmetric-6T) shows the write delay and power decrease by 46% and 35%, respectively, while total power decreases by 52% using the proposed design.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Cumming, Professor David and Cheng, Dr Binjie and Roy, Professor Scott
Authors: Azam, T., Cheng, B., Roy, S., and Cumming, D.R.S.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Electronics Letters
Journal Abbr.:Electron. lett.
Publisher:The Institution of Engineering & Technology
ISSN (Online):1350-911X

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
421321Meeting the design challenges of the nano CMOS electronicsAsen AsenovEngineering & Physical Sciences Research Council (EPSRC)EP/E003125/1Electronic and Nanoscale Engineering