Investigation of geometrical impact on a P+ buried negative capacitance SOI FET

Santra, T., Dixit, A., Jaisawal, R. K., Rathore, S., Sarkhel, S. and Bagga, N. (2022) Investigation of geometrical impact on a P+ buried negative capacitance SOI FET. Microelectronics Journal, 130, 105617. (doi: 10.1016/j.mejo.2022.105617)

Abstract

In this paper, we proposed a novel p+ buried negative capacitance (NC) silicon-on-insulator (SOI) FET and investigated the impact of various device parameter variations on device performances. The placement of the p+ buried layers below the source/drain (S/D) pads restricts the electron conduction in the OFF state, thereby reducing the OFF current (IOFF) with the least effect on the ON-current (ION). The proposed device structure effectively reduces the gate capacitance, providing better DC and analog/RF characteristics. In our proposed study, we separately discussed the effect of NC and impact ionization by turning the models on and off during simulation. Further, we discussed the impact of geometrical parameters of the proposed device, such as channel lengths, channel thickness, extension lengths, etc. on the device's electrical characteristics.

• Item Type: Articles
• Additional Information: N. Bagga greatly acknowledged the support received from the PDPM IIITDM Jabalpur, project title “Design and Performance Investigation of Negative Capacitance Tunnel FET for Digital/Analog Applications,” project no. IIITDMJ/ODRSPC/2022/88.
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Dixit, Mr Ankit

Creator Roles

Dixit, A.: Conceptualization, Methodology, Data curation, Software, Investigation

• Authors: Santra, T., Dixit, A., Jaisawal, R. K., Rathore, S., Sarkhel, S., and Bagga, N.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: Microelectronics Journal
• Publisher: Elsevier
• ISSN: 0026-2692
• Published Online: 31 October 2022
• Copyright Holders: Copyright © 2022 Elsevier
• First Published: First published in Microelectronics Journal 130:105617
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher