Fan, H., Maloberti, F., Li, D., Hu, D., Cen, Y. and Heidari, H. (2017) Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC. In: 20177 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 03-05 Jul 2017, pp. 523-528. (doi: 10.1109/ISVLSI.2017.97)
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146074.pdf - Accepted Version 1MB |
Abstract
This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC.
Item Type: | Conference Proceedings |
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Additional Information: | This work was supported by the National Natural Science Foundation of China (NSFC) under Grant 61401066 and China Postdoctoral Science Foundation under grant 2017M612940 as well as supported by a scholarship from the China Scholarship Council (CSC). |
Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Heidari, Professor Hadi |
Authors: | Fan, H., Maloberti, F., Li, D., Hu, D., Cen, Y., and Heidari, H. |
Subjects: | T Technology > T Technology (General) |
College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering |
ISSN: | 2159-3477 |
Copyright Holders: | Copyright © 2017 IEEE |
First Published: | First published in IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 523-528 |
Publisher Policy: | Reproduced in accordance with the publisher copyright policy |
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