Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Wang, X., Brown, A. R., Cheng, B., Roy, S. and Asenov, A. (2014) Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs. Solid-State Electronics, 98, pp. 99-105. (doi: 10.1016/j.sse.2014.04.017)

96019.pdf - Accepted Version



Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20-nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3-D simulation. It is found that raised drain-bias can exacerbate threshold-voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold-voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de-correlation of DIBL against threshold-voltage.

Item Type:Articles
Additional Information:NOTICE: this is the author’s version of a work that was accepted for publication in Solid-State Electronics. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Solid-State Electronics 98:99-105 2014 DOI: 10.1016/j.sse.2014.04.017
Glasgow Author(s) Enlighten ID:Brown, Mr Andrew and Cheng, Dr Binjie and Roy, Professor Scott and Wang, Dr Xingsheng and Asenov, Professor Asen
Authors: Wang, X., Brown, A. R., Cheng, B., Roy, S., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Solid-State Electronics
Publisher:Elsevier Ltd.
ISSN (Online):1879-2405
Copyright Holders:Copyright © 2014 Elsevier Ltd.
First Published:First published in Solid-State Electronics 98:99-105
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
443791Atomic scale simulation of nanoelectronic devicesAsen AsenovEngineering & Physical Sciences Research Council (EPSRC)EP/E038344/1ENG - ENGINEERING ELECTRONICS & NANO ENG