Alignment verification for electron beam lithography

Thoms, S. , Macintyre, D. S., Docherty, K. E. and Weaver, J. M.R. (2014) Alignment verification for electron beam lithography. Microelectronic Engineering, 123, pp. 9-12. (doi: 10.1016/j.mee.2014.02.005)

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Alignment between lithography layers is essential for device fabrication. A minor defect in a single marker can lead to incorrect alignment and this can be the source of wafer reworks. In this paper we show that this can be prevented by using extra alignment markers to check the alignment during patterning, rather than inspecting vernier patterns after the exposure is completed. Accurate vernier patterns can often only be read after pattern transfer has been carried out. We also show that by using a Penrose tile as a marker it is possible to locate the marker to about 1 nm without fully exposing the resist. This means that the marker can be reused with full accuracy, thus improving the layer to layer alignment accuracy. Lithography tool noise limits the process.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Docherty, Mr Kevin and Weaver, Professor Jonathan and Thoms, Dr Stephen and Macintyre, Dr Douglas
Authors: Thoms, S., Macintyre, D. S., Docherty, K. E., and Weaver, J. M.R.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Microelectronic Engineering
Publisher:Elsevier Science
ISSN (Online):1873-5568
Copyright Holders:Copyright © 2014 Elsevier Science
First Published:First published in Microelectronic Engineering 123:9-12
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher.

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