Drain bias impact on statistical variability and reliability in 20 nm bulk CMOS technology

Wang, X., Brown, A.R., Cheng, B. and Asenov, A. (2013) Drain bias impact on statistical variability and reliability in 20 nm bulk CMOS technology. In: 14th International Conference on Ultimate Integration on Silicon (ULIS), Warwick, UK, 19-21 March 2013. IEEE, pp. 65-68. ISBN 978-1-4673-4800-3 (doi: 10.1109/ULIS.2013.6523492)

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Publisher's URL: http://dx.doi.org/10.1109/ULIS.2013.6523492


tatistical variability and reliability is a critical issue in conventional bulk planar MOSFETs of the 20 nm technology. In this paper we present a comprehensive simulation study of the impact of the drain-bias on the statistical variability in corresponding bulk MOSFETs including the threshold-voltage and the drain-induced barrier lowering (DIBL) which are two important transistor figures of merit. It was found that the threshold-voltage fluctuation increases with drain-bias but the magnitude depends on the dominant statistical variability source including random dopants (RDD), gate line edge roughness (LER), possible metal gate granularity (MGG), and random interface trapped charges (ITC). The correlations between threshold-voltage and DIBL are strongly dependent on the nature of the statistical variability source. RDD, MGG, and ITC are the major contributors to the DIBL variability.

Item Type:Book Sections
Glasgow Author(s) Enlighten ID:Brown, Mr Andrew and Cheng, Dr Binjie and Wang, Dr Xingsheng and Asenov, Professor Asen
Authors: Wang, X., Brown, A.R., Cheng, B., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
443791Atomic scale simulation of nanoelectronic devicesAsen AsenovEngineering & Physical Sciences Research Council (EPSRC)EP/E038344/1ENG - ENGINEERING ELECTRONICS & NANO ENG