Throughput/resource-efficient reconfigurable processor for multimedia applications

Purohit, S., Rahul, S., Margala, M. and Vanderbauwhede, W. (2013) Throughput/resource-efficient reconfigurable processor for multimedia applications. IEEE Transactions on Very Large Scale Integration Systems, 21(7), pp. 1346-1350. (doi: 10.1109/TVLSI.2012.2206063)

Abstract

This brief presents the implementation and evaluation of an 8-bit adaptable processor core to be part of the power-throughput-area efficient multimedia oriented reconfigurable architecture reconfigurable array. The design of the processor core was custom implemented in IBM's 90 nm CMOS technology and occupies 0.115 mm2 silicon area with approximately 70% area utilized by core circuits. The processor shows a peak throughput performance of 75 MOPS/mW. Benchmarking results show estimated throughputs of 9.5, 21.36, 39.78, 170.88, and 4.54 MSamples/s for variants of 2-D discrete cosine transform (DCT), 4 x 4 H.264 integer transform, and 2-D discrete wavelet transform, respectively. Our analysis shows that the proposed design provides approximately 4-8 times higher throughput for 2-D DCT when compared against popular architectures.

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Vanderbauwhede, Professor Wim
• Authors: Purohit, S., Rahul, S., Margala, M., and Vanderbauwhede, W.
• College/School: College of Science and Engineering > School of Computing Science
• Journal Name: IEEE Transactions on Very Large Scale Integration Systems
• Publisher: IEEE
• ISSN: 1063-8210
• Published Online: 25 July 2012