Charge dissipation layer optimisation for nano-scale electron-beam lithography pattern definition onto diamond

Greer, A.I.M. and Moran, D.A.J. (2012) Charge dissipation layer optimisation for nano-scale electron-beam lithography pattern definition onto diamond. Diamond and Related Materials, 29, pp. 13-17. (doi: 10.1016/j.diamond.2012.07.003)

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Abstract

This paper demonstrates that the pattern feature size achieved for electron beam lithography (EBL) on diamond substrates can be minimised through optimisation of the thickness of a surface deposited metallic discharge layer. The purpose and benefits of a charge dissipation layer are presented and the subsequent trade-off with feature size examined. 5 nm of Al is demonstrated to be the optimum thickness of charge dissipation layer for polymethyl methacrylate (PMMA) resist on polycrystalline diamond as the feature size retains a similar variance to thicker layers, has good reproducibility and ultimately produces the smallest feature sizes. PMMA can be used as either a metal deposition mask, or an etch mask for SiO<sub>2</sub> which in turn can be used as an etch mask for diamond. Using this process we have demonstrated pattern transfer and metallisation of features onto diamond and SiO<sub>2</sub> coated diamond down to a dimension of 20 nm.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Greer, Mr Andrew and Moran, Professor David
Authors: Greer, A.I.M., and Moran, D.A.J.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
College of Medical Veterinary and Life Sciences > School of Biodiversity, One Health & Veterinary Medicine
Research Group:Nanoelectronic Diamond Devices and Systems
Journal Name:Diamond and Related Materials
ISSN:0925-9635

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
450861Ultra short gate length diamond FETs for high power/high frequency applicationsDavid MoranEngineering & Physical Sciences Research Council (EPSRC)EP/E054668/1ENG - ENGINEERING ELECTRONICS & NANO ENG