Efficient 2Dmesh Nework on Chip (NoC) considering GALS approach

Rahman, M., Ahmed, I., Rodriguez-Salazar, F. and Islam, N. (2009) Efficient 2Dmesh Nework on Chip (NoC) considering GALS approach. In: Fourth International Conference on Computer Sciences and Convergence Information Technology, 2009. ICCIT '09., Seoul, South Korea, 24-26 Nov 2009, pp. 841-846. ISBN 9781424452446 (doi: 10.1109/ICCIT.2009.303)

Abstract

State of the art VLSI systems are characterised by their small, deca-nano feature size. In order to accommodate the complexity and scalability, a new design paradigm, System on Chip (SoC) has been introduced. Performance and power of giga-scale SoC is ever more communication-dominated. However typical SoC communication infrastructure is based in standard buses and protocols which are difficult to scale to large systems. To solve this problem the Network on Chip (NoC) design paradigm has been introduced, where nodes communicate by exchanging packets through an interconnection network, which consists of routers and networks interfaces. The routers provide reliable data transfer. The network interfaces implement, via connections, high level services, such as transaction ordering, throughput and latency guarantees, and end-to-end flow control. In this research a 2D mesh node communication architecture of NoC is designed and simulated applying the GALS approach. A set of algorithms are also provided for these purpose.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Rodriguez-Salazar, Dr Fernando
• Authors: Rahman, M., Ahmed, I., Rodriguez-Salazar, F., and Islam, N.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• ISBN: 9781424452446