A low-tech solution to avoid the severe impact of transient errors on the IP interconnect

Graham, D., Strid, P., Roy, S. and Rodriguez-Salazar, F. (2009) A low-tech solution to avoid the severe impact of transient errors on the IP interconnect. In: International Conference on Dependable Systems and Networks, 2009. DSN '09. IEEE/IFI2009IEEE/IFIP International Conference on Dependable Systems & Networks, 2009. DSN '09, Lisbon, Portugal, 29 Jun - 2 Jul 2009, pp. 478-483. ISBN 9781424444229 (doi: 10.1109/DSN.2009.5270301)

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Publisher's URL: http://dx.doi.org/10.1109/DSN.2009.5270301

Abstract

There are many sources of failure within a system-on-chip (SoC), so it is important to look beyond the processor core at other components that affect the reliable operation of the SoC, such as the fabric included in every one that connects the IP together. We use ARM's AMBA 3 AXI bus matrix to demonstrate that the impact of errors on the IP interconnect can be severe: possibly causing deadlock or memory corruption. We consider the detection of 1-bit transient faults without changing the IP that connects to the bus matrix or the AMBA 3 standard and without adding extra latency while keeping the performance and area overhead low. We explore what can be done under these constraints and propose a combination of techniques for a low-tech solution to detect these rare events.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Roy, Professor Scott and Rodriguez-Salazar, Dr Fernando
Authors: Graham, D., Strid, P., Roy, S., and Rodriguez-Salazar, F.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
ISBN:9781424444229

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