Tuning of phase-locked loops for power converters under distorted utility conditions

Freijedo, F.D., Doval-Gandoy, J., Lopez, O. and Acha, E. (2009) Tuning of phase-locked loops for power converters under distorted utility conditions. IEEE Transactions on Industry Applications, 45(6), pp. 2039-2047. (doi: 10.1109/TIA.2009.2031790)

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Publisher's URL: http://dx.doi.org/10.1109/TIA.2009.2031790

Abstract

This paper presents a novel approach in the tuning of phase-locked loops (PLLs) for power electronic converters. PLLs are implemented inside a higher level controller to estimate the grid-voltage phase angle and then control the energy transfer between the power converter and the ac mains. The tuning of the PLL is not a trivial task, particularly when considering power-quality phenomena. In a general way, PLLs with a low bandwidth (low-gain PLLs) are required when handling distorted voltages. It is analytically demonstrated in this paper that low-gain PLLs have more tradeoffs than high-gain PLLs ( e. g., PLLs for communications); it is not possible to optimize the settling time for a phase jump without making slower the PLL response to frequency variations. Existing tuning methods do not take into account low-gain features, which may result in nonoptimum designs. The proposed PLL tuning methodology is based on inspection of frequency-domain diagrams and, contrary to the other existing tuning methods, takes into account "low-gain" dynamics. It assures an optimized performance in the presence of any kind of disturbances in the grid. From a practical point of view, the proposed tuning procedure is very intuitive for controller designs. Some significant design examples and experimental results, obtained from a discrete implementation (dSpace platform), are provided in order to validate the theoretical approaches

Item Type:Articles
Keywords:AC/DC power conversion, converter, design, dynamics, energy, features, filters, frequencies, frequency, implementation, performance, phase-locked loops (PLLs), power electronics converters, system, time
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Acha, Prof Enrique
Authors: Freijedo, F.D., Doval-Gandoy, J., Lopez, O., and Acha, E.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Transactions on Industry Applications
ISSN:0093-9994

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