Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs

Moran, D.A.J. et al. (2007) Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs. In: 37th European Solid State Device Research Conference (ESSDERC 2007), Munich, Germany, 11-13 September 2007, pp. 466-469. ISBN 9781424411245 (doi: 10.1109/ESSDERC.2007.4430979)

Abstract

The performance of 300nm, 500nm and 1μm metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-κ (κ=20) dielectric stack grown upon a δ-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 μm to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 μA/μm and extrinsic transconductance of 400 µS/µm are obtained from these devices. Gate leakage current of less than 100pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance submicron enhancement mode III-V MOSFETs reported to date.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Zhou, Dr Haiping and Thayne, Prof Iain and Thoms, Dr Stephen and Moran, Professor David and Li, Dr Xu
• Authors: Moran, D.A.J., Hill, R.J.W., Li, X., Zhou, H., McIntyre, D., Thoms, S., Droopad, R., Zurcher, P., Rajagopalan, K., Abrokwah, J., Passlack, M., and Thayne, I.G.
• Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering; University Centres > Glasgow Materials Research Initiative
• Publisher: IEEE
• ISSN: 1930-8876
• ISBN: 9781424411245
• Copyright Holders: Copyright © 2007 IEEE
• First Published: First published in 37th European Solid State Device Research Conference (ESSDERC 2007)
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher.

Project Code	Award No	Project Name	Principal Investigator	Funder's Name	Funder Ref	Lead Dept
35857	3	Sub 100nm 111-V MOSFET's for Digital Applications	Iain Thayne	Engineering & Physical Sciences Research Council (EPSRC)	GR/S61218/01	Electronic and Nanoscale Engineering