A dynamically reconfigurable hardware co-processor for a multi-standard wireless MAC processor

Nabi, S.W., Wells, C.C. and Vanderbauwhede, W. (2008) A dynamically reconfigurable hardware co-processor for a multi-standard wireless MAC processor. In: Keymeulen, D. (ed.) 2008 NASA/ESA Conference on Adaptive Hardware and Systems, 22-25 June 2008, Noordwijk, The Netherlands. IEEE Computer Society: Los Alamitos, USA, pp. 368-375. ISBN 9780769531663 (doi: 10.1109/AHS.2008.54)

Abstract

The dynamically reconfigurable MAC processor is an innovative architecture specialized for the wireless MAC layer, and aimed at consumer hand-held devices. It is a software/hardware partitioned platform where the microprocessor uses a reconfigurable hardware co-processor to delegate critical tasks. This allows the microprocessor to handle fast and complex MAC protocols while clocking at relatively slow speeds, thus consuming less power. The architecture on the whole is designed to be dynamically reconfigurable. It will handle data streams of multiple (up to 3) different protocol standards, by reconfiguring on a packet-by-packet basis. Results of simulation of packet transmission and reception on a prototype Simulink model indicate that a packet to packet reconfiguration for three concurrent data streams, while meeting protocol real-time requirements, will indeed be possible.

• Item Type: Book Sections
• Status: Published
• Glasgow Author(s) Enlighten ID: Vanderbauwhede, Professor Wim and Wells, Dr Cade
• Authors: Nabi, S.W., Wells, C.C., and Vanderbauwhede, W.
• Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
• College/School: College of Science and Engineering > School of Computing Science
• Publisher: IEEE Computer Society
• ISBN: 9780769531663