A performance model of multicast communication in wormhole-routed networks on-chip

Moadeli, M. and Vanderbauwhede, W. (2009) A performance model of multicast communication in wormhole-routed networks on-chip. In: IEEE International Symposium on Parallel & Distributed Processing, 2009. IPDPS 2009., Rome, Italy, 23-29 May 2009, pp. 1-8. ISBN 9781424437511 (doi: 10.1109/IPDPS.2009.5161177)

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Publisher's URL: http://dx.doi.org/10.1109/IPDPS.2009.5161177

Abstract

Collective communication operations form a part of overall traffic in most applications running on platforms employing direct interconnection networks. This paper presents a novel analytical model to compute communication latency of multicast as a widely used collective communication operation. The novelty of the model lies in its ability to predict the latency of the multicast communication in wormhole-routed architectures employing asynchronous multi-port routers scheme. The model is applied to the Quarc NoC and its validity is verified by comparing the model predictions against the results obtained from a discrete-event simulator developed using OMNET++.

Item Type:Conference Proceedings
Additional Information:Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Professor Wim and Moadeli, Mr Mahmoud
Authors: Moadeli, M., and Vanderbauwhede, W.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society
ISBN:9781424437511
Copyright Holders:Copyright © 2009 IEEE
First Published:First published in Proceedings of IEEE International Symposium on Parallel and Distributed Processing, 2009. IPDPS 2009.
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher.

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
389341A novel service-based system on a chip architecture using on chip networks with smart packets and dynamically reconfigurable logicWim VanderbauwhedeEngineering & Physical Sciences Research Council (EPSRC)GR/T03239/01COM - COMPUTING SCIENCE