Design and implementation of the Quarc network on-chip

Moadeli, M., Maji, P.P. and Vanderbauwhede, W. (2009) Design and implementation of the Quarc network on-chip. In: 2009 IEEE International Symposium on Parallel and Distributed Processing, 23-29 May 2009, Rome, Italy. IEEE Computer Society: Piscataway, N.J., USA, pp. 1-9. ISBN 9781424437511 (doi: 10.1109/IPDPS.2009.5161210)

Abstract

Networks-on-Chip (NoC) have emerged as alternative to buses to provide a packet-switched communication medium for modular development of large Systems-on-Chip. However, to successfully replace its predecessor, the NoC has to be able to efficiently exchange all types of traffic including collective communications. The latter is especially important for e.g. cache updates in multicore systems. The Quarc NoC architecture has been introduced as a Networks-on-Chip which is highly efficient in exchanging all types of traffic including broadcast and multicast. In this paper we present the hardware implementation of the switch architecture and the network adapter (transceiver) of the Quarc NoC. Moreover, the paper presents an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs implemented in Verilog targeting the Xilinx Virtex FPGA family. We demonstrate a dramatic improvement in performance over the Spidergon especially for broadcast traffic, at no additional hardware cost.

• Item Type: Book Sections
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• Status: Published
• Glasgow Author(s) Enlighten ID: Vanderbauwhede, Professor Wim and Moadeli, Mr Mahmoud
• Authors: Moadeli, M., Maji, P.P., and Vanderbauwhede, W.
• Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
• College/School: College of Science and Engineering > School of Computing Science
• Publisher: IEEE Computer Society
• ISBN: 9781424437511
• Copyright Holders: Copyright © 2009, IEEE.
• First Published: First published in Proceedings of 2009 IEEE International Symposium on Parallel and Distributed Processing, 23-29 May 2009, Rome, Italy : 1-9
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher.

Project Code	Award No	Project Name	Principal Investigator	Funder's Name	Funder Ref	Lead Dept
38934	1	A novel service-based system on a chip architecture using on chip networks with smart packets and dynamically reconfigurable logic	Wim Vanderbauwhede	Engineering & Physical Sciences Research Council (EPSRC)	GR/T03239/01	COM - COMPUTING SCIENCE