On the sub-nm EOT scaling of high-kappa gate stacks

Markov, S., Roy, S., Fiegna, C., Sangiorgi, E. and Asenov, A. (2008) On the sub-nm EOT scaling of high-kappa gate stacks. In: International Conference on the Ultimate Integration of Silicon, Udine, Italy, 13-14 Mar 2008,

Abstract

Incorporating recent data for the Si/SiO2 and SiO2/HfO2 interface properties, we simulate the impact of band-gap and permittivity transitions on high-kappa. (HK) gate-stack (GS) metal-oxide-semiconductor (MOS) devices, scaled according to the requirements for effective oxide thickness (EOT) reduction in bulk MOSFETs. Si/SiO2 transition effects dominate, lowering the EOT, increasing over 10 times gate leakage, and shifting over 20% of electrons from the 2-fold, to the 4-fold degenerate valley. Accounting for the interface transition effects is important for accurate HKGS device characterisation and predictive modelling

• Item Type: Conference Proceedings
• Status: Published
• Refereed: No
• Glasgow Author(s) Enlighten ID: Markov, Dr Stanislav and Roy, Professor Scott and Asenov, Professor Asen
• Authors: Markov, S., Roy, S., Fiegna, C., Sangiorgi, E., and Asenov, A.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering