Simulation of strain enhanced variability in nMOSFETs

Wang, X., Cheng, B., Roy, S. and Asenov, A. (2008) Simulation of strain enhanced variability in nMOSFETs. In: 9th International Conference on Ultimate Integration of Silicon, 2008. ULIS 2008., Udine, Italy, 12-14 March 2008, pp. 89-92. (doi: 10.1109/ULIS.2008.4527147)

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We present a 3D simulation methodology aiming to capture the impact of strain on the line edge roughness (LER) induced variability in nMOSFETs. It includes both process and device simulation calibrated in respect of real 35 nm gate length nMOSFETs. Statistical LER of the gate pattern is introduced at the process simulation stage, and the impact of strain on the LER induced variability is investigated in Silicon nMOSFETs for the first time. Gate LER introduces both doping profile variability, and variability in the strain distribution in the channel, both contributing to the statistical variability in device electrical characteristics.

Item Type:Conference Proceedings
Glasgow Author(s) Enlighten ID:Cheng, Dr Binjie and Roy, Professor Scott and Wang, Dr Xingsheng and Asenov, Professor Asen
Authors: Wang, X., Cheng, B., Roy, S., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

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