Capacitance variability of short range interconnects

Drysdale, T. D., Brown, A. R., Roy, G., Roy, S. and Asenov, A. (2008) Capacitance variability of short range interconnects. Journal of Computational Electronics, 7(3), pp. 124-127. (doi: 10.1007/s10825-007-0154-6)

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Line edge roughness (LER) in end-of-the-roadmap integrated circuit interconnects causes variability in their resistance R, capacitance C and hence also their RC delay. We present an analysis of LER-induced variability of resistance, capacitance and delay of short-range interconnects within standard cells at the 32, 22 and 18 out technology nodes using both a commercial RC extraction tool as well as a fast quasi-analytical (QA) method. Our QA method includes size dependent resistivity which, when coupled with LER, reveals increased resistance variability and total resistance in interconnects at these technology nodes. For example, the QA method predicts variability of 52% in resistance, 16% in capacitance and 36% in RC delay. When LER is the dominant source of variability there is a correlation of -0.8 between resistance and capacitance. Our results indicate interconnect variability is a significant and worsening problem, which should be included in statistical models of standard cells.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Drysdale, Dr Timothy and Roy, Dr Gareth and Brown, Mr Andrew and Roy, Professor Scott and Asenov, Professor Asen
Authors: Drysdale, T. D., Brown, A. R., Roy, G., Roy, S., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Journal of Computational Electronics

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