PBTI/NBTI-related variability in TB-SOI and DG MOSFETs

Cheng, B., Brown, A.R., Roy, S. and Asenov, A., (2010) PBTI/NBTI-related variability in TB-SOI and DG MOSFETs. IEEE Electron Device Letters, 31(5), pp. 408-410. (doi: 10.1109/LED.2010.2043812)

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We study positive bias temperature instability/negative bias temperature instability (PBTI/NBTI)-related aging-dependent statistical variability (SV) in 32-nm thin-body silicon-on-insulator (TB-SOI) and 22-nm double-gate (DG) MOSFETs using comprehensive 3-D numerical simulation. Results indicate that a high degree of PBTI/NBTI degradation can introduce a similar level of SV as the variability in the initial "virgin" devices introduced by random discrete dopants and line edge roughness. Simulations have shown that the TB-SOI and the DG MOSFETs have different susceptibilities to PBTI/NBTI-induced variability.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Brown, Mr Andrew and Cheng, Dr Binjie and Roy, Professor Scott and Asenov, Professor Asen
Authors: Cheng, B., Brown, A.R., Roy, S., and Asenov, A.,
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Electron Device Letters
Publisher:Institute of Electrical and Electronics Engineers
ISSN (Online):1558-0563

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