High performance MOSFET scaling study from bulk 45nm technology generation

Wang, X., Roy, S. and Asenov, A. (2008) High performance MOSFET scaling study from bulk 45nm technology generation. In: Proceeding of the 9th International Conference on Solid-State and Integrated-Circuit Technology: 20-23 October 2008, Beijing, China. IEEE Computer Society: Piscataway, N.J., USA, pp. 484-487. ISBN 9781424421855 (doi: 10.1109/ICSICT.2008.4734586)

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This paper presents a MOSFET scaling study based on the current 45 nm technology generation. The study is based on a real 35 nm gate length design, to which the simulation tools are carefully calibrates. Features such as strain enhancement, and high-kappa / metal gates are included in the simulations, which then exhibit equivalent performance to state-of-the-art bulk devices. Realistic choices of device dimensions and doping profiles are made for the scaled devices, which indeed demonstrate the benefits from scaling and the introduction of technology boosters.

Item Type:Book Sections
Keywords:Cmos, decananometer, design, device, devices, engineering, enhancement, features, generation, intrinsic parameter fluctuations, MOSFET, performance, physics, simulation, strain, technologies, technology, transistors
Glasgow Author(s) Enlighten ID:Roy, Professor Scott and Wang, Dr Xingsheng and Asenov, Professor Asen
Authors: Wang, X., Roy, S., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Publisher:IEEE Computer Society

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