Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors

Li, X. , Hill, R.J.W., Longo, P., Holland, M.C., Zhou, H., Thoms, S. , Macintyre, D.S. and Thayne, I.G. (2009) Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 27(6), pp. 3153-3157. (doi: 10.1116/1.3256624)

Abstract

This article describes a process flow that has enabled the first demonstration of functional, fully self-aligned 100 nm enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with GaxGdyOz as high-kappa dielectric, Pt/W as metal gate stack, and SiN as sidewall spacers. The flow uses blanket metal and dielectric deposition and low damage dry etch modules. As a consequence, no critical dimension lift-off processes are required. Encouraging data are presented for 100 nm gate length devices including threshold voltage of 0.32 V, making these the shortest, fully self-aligned gate length enhancement mode III-V MOSFETs reported to date. This work is a significant step forward to the demonstration of high performance "siliconlike" III-V MOSFETs.

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Zhou, Dr Haiping and Thayne, Prof Iain and Longo, Dr Paolo and Thoms, Dr Stephen and Hill, Mr Richard and Li, Dr Xu and Macintyre, Dr Douglas and Holland, Dr Martin
• Authors: Li, X., Hill, R.J.W., Longo, P., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S., and Thayne, I.G.
• Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
• ISSN: 1071-1023
• ISSN (Online): 1520-8567

Project Code	Award No	Project Name	Principal Investigator	Funder's Name	Funder Ref	Lead Dept
45248	1	Silicon compatible process modules for III-V electronic devices.	Iain Thayne	Engineering & Physical Sciences Research Council (EPSRC)	EP/F002610/1	Electronic and Nanoscale Engineering