Evaluation of statistical variability in 32 and 22 nm technology generation LSTP MOSFETs

Cheng, B., Roy, S., Brown, A.R., Millar, C. and Asenov, A. (2009) Evaluation of statistical variability in 32 and 22 nm technology generation LSTP MOSFETs. Solid-State Electronics, 53(7), pp. 767-772. (doi: 10.1016/j.sse.2009.03.008)

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The quantitative evaluation of the impact of key sources of static and dynamic statistical variability (SV) are presented for LSTP nMOSFETs corresponding to 32 nm and 22 nm technology generation transistors with thin-body (TB) Sol and double gate (DG) architectures, respectively. The simulation results indicate that TB SOI and DG devices are not only more resistant to random dopant induced variability compared to their bulk counterparts, but are also more tolerant to line edge roughness induced variability. However, the improved static SV performance shifts the emphasis to dynamic SV introduced by trapped charge associated with aging processes.

Item Type:Articles
Keywords:Decananometer mosfets, device, devices, edge roughness, engineering, England, generation, impact, intrinsic parameter fluctuations, line edge roughness, MOSFET, MOSFETSs, performance, physics, random discrete dopant, roughness, science, simulation, SOI, statistical variability, technologies, technology, thin-body devices, transistor, transistors, trapped charge, variability
Glasgow Author(s) Enlighten ID:Millar, Dr Campbell and Brown, Mr Andrew and Cheng, Dr Binjie and Roy, Professor Scott and Asenov, Professor Asen
Authors: Cheng, B., Roy, S., Brown, A.R., Millar, C., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Solid-State Electronics
ISSN (Online):1879-2405
Published Online:25 April 2009

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