Symmetry in temporal logic model checking

Miller, A., Donaldson, A. and Calder, M. (2006) Symmetry in temporal logic model checking. ACM Computing Surveys, 38(3), (doi: 10.1145/1132960.1132962)

Abstract

Temporal logic model checking involves checking the state-space of a model of a system to determine whether errors can occur in the system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.

• Item Type: Articles
• Keywords: theory, verification, model checking, symmetry, quotient graph
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Calder, Professor Muffy and Miller, Professor Alice
• Authors: Miller, A., Donaldson, A., and Calder, M.
• Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
• College/School: College of Science and Engineering > School of Computing Science
• Journal Name: ACM Computing Surveys
• Publisher: ACM Press
• ISSN: 0360-0300
• Copyright Holders: Copyright © 2006 ACM Press
• First Published: First published in ACM Computing Surveys 38(3)
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher