Simulations of sub-100nm strained Si MOSFETs with high k gate stacks

Yang, L., Watling, J., Adamu-Lema, F., Asenov, A. and Barker, J. (2004) Simulations of sub-100nm strained Si MOSFETs with high k gate stacks. In: International workshop on Computational Electronics, IWCE-10, West Lafeyette, USA,

Full text not currently available from Enlighten.


Item Type:Conference Proceedings
Keywords:Atomistic, Channel, Flow, Fluctuations, Gate, MOSFET, MOSFETS, Si, Silicon, Simulation, Stacks, Strained Si, Strained-Si
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Barker, Professor John and Watling, Dr Jeremy and Asenov, Professor Asen
Authors: Yang, L., Watling, J., Adamu-Lema, F., Asenov, A., and Barker, J.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Publisher:IEEE

University Staff: Request a correction | Enlighten Editors: Update this record