Hardware/Software Co-Design of Edge DNN Accelerators with TFLite

Haris, J., Gibson, P., Cano, J. , Agostini, N. B. and Kaeli, D. (2022) Hardware/Software Co-Design of Edge DNN Accelerators with TFLite. 18th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Fiuggi, Italy, 10-16 July 2022.

Abstract

In this work we discuss SECDA-TFLite, a open-source toolkit for developing DNN hardware accelerators, integrated within the TFLite DNN inference framework. The toolkit leverages the principles of SECDA, a hardware/software co-design methodology which reduces the design time of optimized DNN inference accelerators on edge devices with FPGAs. Utilizing SECDA-TFLite, we further reduce the initial setup costs associated with integrating a new accelerator design within a target DNN framework, allowing developers to focus on the design. SECDA-TFLite also includes modules for cost-effective SystemC simulation, profiling, and AXI-based data communication. Additionally, we briefly cover our case study, where we use SECDA-TFLite to efficiently develop three different DNN accelerator designs on a PYNQ-Z1 board. We evaluate the three accelerator designs across five common CNN models and two BERT-based models, achieving an average performance speedup across models of up to 2.9x for the CNN models and an average speedup of up to 2.5x for the BERT-based models.

• Item Type: Conference or Workshop Item
• Keywords: DNN accelerator design, design methodology, hardware-software co-design, systemC, simulation, HLS
• Status: Published
• Refereed: No
• Glasgow Author(s) Enlighten ID: Cano Reyes, Dr Jose and Haris, Jude and Gibson, Perry
• Authors: Haris, J., Gibson, P., Cano, J., Agostini, N. B., and Kaeli, D.
• College/School: College of Science and Engineering > School of Computing Science
• Copyright Holders: Copyright © 2022 HiPEAC
• Publisher Policy: Reproduced with the permission of the publisher

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