XNOR-Nets with SETs: proposal for a binarised convolution processing elements with Single-Electron Transistors

Bheemireddy, V. (2022) XNOR-Nets with SETs: proposal for a binarised convolution processing elements with Single-Electron Transistors. Scientific Reports, 12, 9953. (doi: 10.1038/s41598-022-13180-7) (PMID:35705581) (PMCID:PMC9200707)

Abstract

Deep neural network (DNN) and Convolution neural network (CNN) algorithms have significantly increased the accuracies in cutting-edge large-scale image recognition and natural-language processing tasks. Generally, such neural nets are implemented on power-hungry GPUs, beyond the reach of low-power edge-devices. The binary neural nets have been proposed recently, where both the input activations and weights are constrained to + 1 and − 1 to address this challenge. Here in the present proof-of-concept study, we propose a simple class of mixed-signal circuits composed of single-electron devices and exploit the nonlinear Coulomb staircase phenomena to alleviate the challenges of binarised deep learning hardware accelerators. In particular, through SPICE modeling, we demonstrate the realisation of space-time-energy efficient XNOR-Accumulation (XAC) operation, reconfigurabilty of XAC circuit to perform 1D convolution and a busbar design to augment a contemporary accelerator. These nanoscale circuits could be readily fabricated and may potentially be deployed in low-power deep-learning systems.

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Bheemireddy, Varun
• Authors: Bheemireddy, V.
• College/School: College of Science and Engineering
• Journal Name: Scientific Reports
• Publisher: Nature Research
• ISSN: 2045-2322
• ISSN (Online): 2045-2322
• Copyright Holders: Copyright © 2022 The Authors
• First Published: First published in Scientific Reports 12(1):9953
• Publisher Policy: Reproduced under a Creative Commons License