Gauhar, G. A., Chenchety, A., Yenugula, H., Georgiev, V. , Asenov, A. and Badami, O. (2022) Study of gate current in advanced MOS architectures. Solid-State Electronics, 194, 108345. (doi: 10.1016/j.sse.2022.108345)
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Abstract
We have carried out a comprehensive study of the gate current (IG) in advanced MOS architectures for different gate lengths and cross-section areas using an in-house simulation tool. We have considered only direct tunneling under the assumption that trap concentration and therefore the trap assisted current would be small in a matured technology. We have also studied the impact of the interfacial (IL) SiO2 layer on the gate current in the high- gate stack. Our results suggest that IL leads to an increase in the gate current for equivalent EOT. They also highlight that reduction in the cross-section area leads to a significant increase in the IG.
Item Type: | Articles |
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Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Asenov, Professor Asen and Badami, Mr Oves and Georgiev, Professor Vihar |
Authors: | Gauhar, G. A., Chenchety, A., Yenugula, H., Georgiev, V., Asenov, A., and Badami, O. |
College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering |
Journal Name: | Solid-State Electronics |
Publisher: | Elsevier |
ISSN: | 0038-1101 |
ISSN (Online): | 1879-2405 |
Published Online: | 25 April 2022 |
Copyright Holders: | Copyright © 2022 Published by Elsevier Ltd. |
First Published: | First published in Solid-State Electronics 194: 108345 |
Publisher Policy: | Reproduced in accordance with the publisher copyright policy |
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