Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation--part II: CNT interconnect optimization

Chen, R. et al. (2022) Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation--part II: CNT interconnect optimization. IEEE Transactions on Very Large Scale Integration Systems, 30(4), pp. 440-448. (doi: 10.1109/TVLSI.2022.3146064)

Abstract

The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a carbon nanotube (CNT) SRAM array composed of the schematically optimized CNFET SRAM and CNT interconnects. We consider the interconnects inside the CNFET SRAM cell composed of metallic single-wall CNT (M-SWCNT) bundles to represent the metal layers 0 and 1 (M0 and M1). We investigate the layout structure of CNFET SRAM cell considering CNFET devices, M-SWCNT interconnects, and metal electrode Palladium with CNT (Pd-CNT) contacts. Two versions of cell layout designs are explored and compared in terms of performance, stability, and power efficiency. Furthermore, we implement a 16 Kbit SRAM array composed of the proposed CNFET SRAM cells, multiwall CNT (MWCNTs) inter-cell interconnects and Pd-CNT contacts. Such an array shows significant advantages, with the read and write overall energy-delay product (EDP), static power consumption, and core area of 0.28x, 0.52x, and 0.76x respectively to 7-nm FinFET-SRAM array with copper interconnects, whereas the read and write static noise margins are 6% and 12% respectively larger than the FinFET counterpart.

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Asenov, Professor Asen and Georgiev, Professor Vihar
• Authors: Chen, R., Chen, L., Liang, J., Cheng, Y., Elloumi, S., Lee, J., Xu, K., Georgiev, V. P., Ni, K., Debacker, P., Asenov, A., and Todri-Sanial, A.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: IEEE Transactions on Very Large Scale Integration Systems
• Publisher: IEEE
• ISSN: 1063-8210
• ISSN (Online): 1557-9999
• Published Online: 14 February 2022
• Copyright Holders: Copyright © 2022 IEEE
• First Published: First published in IEEE Transactions on Very Large Scale Integration Systems 30(4): 440-448
• Publisher Policy: Reproduced in accordance with the publisher copyright policy

Project Code	Award No	Project Name	Principal Investigator	Funder's Name	Funder Ref	Lead Dept
172264		CONNECT	Asen Asenov	European Commission (EC)	688612	ENG - Electronics & Nanoscale Engineering