An efficient analog circuit sizing method based on machine learning assisted global optimization

Budak, A., Gandara, M., Shi, W., Pan, D., Sun, N. and Liu, B. (2022) An efficient analog circuit sizing method based on machine learning assisted global optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(5), pp. 1209-1221. (doi: 10.1109/TCAD.2021.3081405)

Abstract

Machine learning-assisted global optimization methods for speeding up analog integrated circuit sizing is attracting much attention. However, often a few typical analog IC design specifications are considered in most relevant research. When considering the complete set of specifications, two main challenges are yet to be addressed: (1) The prediction error for some performances may be large and the prediction error is accumulated by many performances. This may mislead the optimization and fail the sizing, especially when the specifications are stringent. (2) The machine learning cost could be high considering the number of specifications, considerably canceling out the time saved. A new method, called Efficient Surrogate Model-assisted Sizing Method for High-performance Analog Building Blocks (ESSAB), is proposed in this paper to address the above challenges. The key innovations include a new candidate design ranking method and a new artificial neural network model construction method for analog circuit performances. Experiments using two amplifiers and a comparator with a complete set of stringent design specifications show the advantages of ESSAB.

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Liu, Dr Bo and Budak, Ahmet
• Authors: Budak, A., Gandara, M., Shi, W., Pan, D., Sun, N., and Liu, B.
• College/School: College of Science and Engineering > School of Engineering > Systems Power and Energy
• Journal Name: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Publisher: IEEE
• ISSN: 0278-0070
• ISSN (Online): 1937-4151
• Published Online: 18 May 2021
• Copyright Holders: Copyright © 2021 Crown Copyright
• First Published: First published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41(5): 1209-1221
• Publisher Policy: Reproduced in accordance with the publisher copyright policy