Dynamic Simulation of Write ‘1’Operation in the Bi-stable 1-Transistor SRAM Cell

Dutta, T. , Adamu-Lema, F., Asenov, A. , Widjaja, Y. and Nebesnyi, V. (2020) Dynamic Simulation of Write ‘1’Operation in the Bi-stable 1-Transistor SRAM Cell. In: 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kobe, Japan, 23 Sept.-6 Oct. 2020, pp. 237-240. ISBN 9784863487635 (doi: 10.23919/SISPAD49475.2020.9241653)

Abstract

For the first time, physical insights into the writing process in the bi-stable 1-transistor SRAM cells are provided using dynamic (time dependent) TCAD simulations. The simulations are based on 28 nm planar CMOS technology, and the setup is carefully calibrated against available experimental data. Based on the simulations, we were able to identify clearly the mechanisms involved in the write `1' operation. The dependence of the writing process on drain and gate bias conditions was also investigated.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Asenov, Professor Asen and Dutta, Dr Tapas and Adamu-Lema, Dr Fikru
• Authors: Dutta, T., Adamu-Lema, F., Asenov, A., Widjaja, Y., and Nebesnyi, V.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Research Group: Device Modeling Group
• ISSN: 1946-1577
• ISBN: 9784863487635
• Copyright Holders: Copyright © 2020 IEEE
• First Published: First published in 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
• Publisher Policy: Reproduced in accordance with the publisher copyright policy