A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems

Liu, B. , Messaoudi, J. and Gielen, G. (2012) A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems. In: 2012 Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, 12-16 Mar 2012, ISBN 9781457721458 (doi: 10.1109/DATE.2012.6176569)

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Yield estimation for analog integrated circuits remains a time-consuming operation in variation-aware sizing. State-of-the-art statistical methods such as ranking-integrated Quasi-Monte-Carlo (QMC), suffer from performance degradation if the number of effective variables is large (as typically is the case for realistic analog circuits). To address this problem, a new method, called AYLeSS, is proposed to estimate the yield of analog circuits by introducing Latin Supercube Sampling (LSS) technique from the computational statistics field. Firstly, a partitioning method is proposed for analog circuits, whose purpose is to appropriately partition the process variation variables into low-dimensional sub-groups fitting for LSS sampling. Then, randomized QMC is used in each sub-group. In addition, the way to randomize the run order of samples in Latin Hypercube Sampling (LHS) is used for the QMC sub-groups. AYLeSS is tested on 4 designs of 2 example circuits in 0.35μm and 90nm technologies with yield from about 50% to 90%. Experimental results show that AYLeSS has approximately a 2 times speed enhancement compared with the best state-of-the-art method.

Item Type:Conference Proceedings
Glasgow Author(s) Enlighten ID:Liu, Dr Bo
Authors: Liu, B., Messaoudi, J., and Gielen, G.
College/School:College of Science and Engineering > School of Engineering
Published Online:03 April 2012

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