Layer-by-layer-assembled reduced graphene oxide/gold nanoparticle hybrid double-floating-gate structure for low-voltage flexible flash memory

Han, S.-T., Zhou, Y., Wang, C., He, L., Zhang, W. and Roy, V.A.L. (2013) Layer-by-layer-assembled reduced graphene oxide/gold nanoparticle hybrid double-floating-gate structure for low-voltage flexible flash memory. Advanced Materials, 25(6), pp. 872-877. (doi: 10.1002/adma.201203509) (PMID:23125077)

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Abstract

A hybrid double-floating-gate flexible memory device by utilizing an rGO-sheet monolayer and a Au NP array as upper and lower floating gates is reported. The rGO buffer layer acts as a charge-trapping layer and introduces an energy barrier between the Au NP lower floating gate and the channel. The proposed memory device demonstrates a strong improvement in both field-effect-transistor (FET) and memory characteristics.

Item Type:Articles
Additional Information:We acknowledge grants from City University of Hong Kong's Strategic Research Grant Project no. 7002724 and the Research Grants Council of the Hong Kong Special Administrative Region (Project No.T23ā€713/11 and AoE/Pā€03/08). The authors acknowledge Tak Fu Hung and Tsz Chun Lau of City University of Hong Kong for their technical assistance.
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Vellaisamy, Professor Roy
Authors: Han, S.-T., Zhou, Y., Wang, C., He, L., Zhang, W., and Roy, V.A.L.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Advanced Materials
Publisher:Wiley - V C H Verlag GmbH & Co. KGaA
ISSN:0935-9648
ISSN (Online):1521-4095
Published Online:05 November 2012

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