Modelling HW/SW Co-Designed Processors

Cano, J. et al. (2012) Modelling HW/SW Co-Designed Processors. 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Fiuggi, Italy, 08-14 Jul 2012.

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This paper presents DARCO, an extensible platform for modelling HW/SW co-designed processors with different guest and host ISAs. Its Emulation Software Layer (ESL) provides staged compilation, which translates and optimizes x86 binaries to run on a PowerPC processor. In addition to the functional models, DARCO provides timing simulators and a powerful debugging toolchain. DARCO has a functional emulation speed of 8 million x86 instructions per second.

Item Type:Conference or Workshop Item
Glasgow Author(s) Enlighten ID:Cano Reyes, Dr Jose
Authors: Cano, J., Brankovic, A., Kumar, R., Zivanovic, D., Pavlou, D., Stavrou, K., Gibert, E., Martinez, A., Dot, G., Latorre, F., Barcelo, A., and Gonzalez, A.
College/School:College of Science and Engineering > School of Computing Science

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