Spidergon STNoC Design Flow

Dubois, F., Cano, J. , Marcello, C., Flich, J. and Pétrot, F. (2011) Spidergon STNoC Design Flow. In: NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, PA, USA, 01-04 May 2011, pp. 267-268. ISBN 9781450307208 (doi: 10.1145/1999946.1999994)

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In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.

Item Type:Conference Proceedings
Glasgow Author(s) Enlighten ID:Cano Reyes, Dr Jose
Authors: Dubois, F., Cano, J., Marcello, C., Flich, J., and Pétrot, F.
College/School:College of Science and Engineering > School of Computing Science
Journal Name:NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

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