Efficient Routing Implementation in Complex Systems-on-Chip Designs

Cano, J. , Flich, J., Duato, J., Coppola, M. and Locatelli, R. (2011) Efficient Routing Implementation in Complex Systems-on-Chip Designs. In: NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, PA, USA, 01-04 May 2011, pp. 1-8. ISBN 9781450307208 (doi: 10.1145/1999946.1999948)

Full text not currently available from Enlighten.


In application-specific SoCs, the irregularity of the topology ends up in a complex implementation of the routing algorithm, usually relying on routing tables implemented with memory structures. As system size increases, the routing table increases in size with non-negligible impact on power, area and latency overheads. In this paper we present a routing implementation for application-specific SoCs able to implement in an efficient manner (without requiring routing tables and using a small logic block in every switch) a routing algorithm in these irregular networks. The mechanism relies on a tool that maps the initial irregular topology of the SoC system into a logical regular structure where the mechanism can be applied. We provide details on the mapping tool as well the proposed routing mechanism. Evaluation results show the effectiveness of the mapping tool as well as the low area and timing requirements of the mechanism. With the mapping tool and the routing mechanism complex irregular SoC topologies can now be supported without the use of routing tables.

Item Type:Conference Proceedings
Glasgow Author(s) Enlighten ID:Cano Reyes, Dr Jose
Authors: Cano, J., Flich, J., Duato, J., Coppola, M., and Locatelli, R.
College/School:College of Science and Engineering > School of Computing Science
Journal Name:NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

University Staff: Request a correction | Enlighten Editors: Update this record