Efficient routing in heterogeneous SoC designs with small implementation overhead

Cano, J. , Flich, J., Roca, A., Duato, J., Coppola, M. and Locatelli, R. (2014) Efficient routing in heterogeneous SoC designs with small implementation overhead. IEEE Transactions on Computers, 63(3), pp. 557-569. (doi: 10.1109/TC.2012.299)

177448.pdf - Accepted Version



In application-specific SoCs, the irregularity of the topology ends up in a complex and customized implementation of the routing algorithm, usually relying on routing tables implemented with memory structures at source end nodes. As system size increases, the routing tables also increase in size with nonnegligible impact on power, area, and latency overheads. In this paper, we present a routing implementation for application-specific SoCs able to implement in an efficient manner (with no routing tables and using a small logic block in every switch) a deadlock-free routing algorithm in these irregular networks. The mechanism relies on a tool that maps the initial irregular topology of the SoC system into a logical regular structure where the mechanism can be applied. We provide details for both the mapping tool and the proposed routing mechanism. Evaluation results show the effectiveness of the mapping tool as well as the low area and timing requirements of the mechanism. With the mapping tool and the routing mechanism, complex irregular SoC topologies can now be supported without the need for routing tables.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Cano Reyes, Dr Jose
Authors: Cano, J., Flich, J., Roca, A., Duato, J., Coppola, M., and Locatelli, R.
College/School:College of Science and Engineering > School of Computing Science
Journal Name:IEEE Transactions on Computers
ISSN (Online):1557-9956
Published Online:24 December 2012
Copyright Holders:Copyright © 2014 IEEE
First Published:First published in IEEE Transactions on Computers 63(3): 557-569
Publisher Policy:Reproduced in accordance with the publisher copyright policy

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