Impact of stress in ICP-CVD SiN x passivation films on the leakage current in AlGaN/GaN HEMTs

Cho, S.-J., Li, X. , Guiney, I., Floros, K., Hemakumara, D., Wallis, D.J., Humphreys, C. and Thayne, I.G. (2018) Impact of stress in ICP-CVD SiN x passivation films on the leakage current in AlGaN/GaN HEMTs. Electronics Letters, 54(15), pp. 947-949. (doi: 10.1049/el.2018.1097)

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Abstract

The impact of the stress in room temperature inductively coupled plasma chemical vapour deposited (ICP-CVD) SiN x surface passivation layers on off-state drain ( I DS-off) and gate leakage currents ( I GS) in AlGaN/GaN high electron mobility transistors (HEMTs) is reported. I DS-off and I GS in 2 μm gate length devices were reduced by up to four orders of magnitude to ∼10 pA/mm using a compressively stressed bilayer SiN x passivation scheme. In addition, I on/ I off of ∼10 11 and subthreshold slope of 68 mV/dec were obtained using this strain engineered surface passivation approach.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Thayne, Prof Iain and HEMAKUMARA, Dilini and FLOROS, KONSTANTINOS and Li, Dr Xu and Cho, Dr Sung-Jin
Authors: Cho, S.-J., Li, X., Guiney, I., Floros, K., Hemakumara, D., Wallis, D.J., Humphreys, C., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Electronics Letters
Publisher:Institution of Engineering and Technology
ISSN:0013-5194
ISSN (Online):1350-911X
Published Online:29 May 2018
Copyright Holders:Copyright © 2018 The Institution of Engineering and Technology
First Published:First published in Electronics Letters 54(15): 947-949
Publisher Policy:Reproduced under a Creative Commons License

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
600761Silicon Compatible GaN Power ElectronicsIain ThayneEngineering and Physical Sciences Research Council (EPSRC)EP/K014471/1ENG - ENGINEERING ELECTRONICS & NANO ENG