Carrillo-Nuñez, H., Mirza, M. M. , Paul, D. J. , MacLaren, D. A. , Asenov, A. and Georgiev, V. P. (2018) Impact of randomly distributed dopants on Ω-gate junctionless silicon nanowire transistors. IEEE Transactions on Electron Devices, 65(5), pp. 1692-1698. (doi: 10.1109/TED.2018.2817919)
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Abstract
This paper presents experimental and simulation analysis of an Ω-shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for the 1.8-V gate overdrive with an OFF-current set at 100 nA/μm. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current-voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ID-VGs characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ID-VGs characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs.
| Item Type: | Articles |
|---|---|
| Status: | Published |
| Refereed: | Yes |
| Glasgow Author(s) Enlighten ID: | Mirza, Dr Muhammad M A and Carrillo-Nunez, Dr Hamilton and MacLaren, Professor Donald and Georgiev, Professor Vihar and Paul, Professor Douglas and Asenov, Professor Asen |
| Authors: | Carrillo-Nuñez, H., Mirza, M. M., Paul, D. J., MacLaren, D. A., Asenov, A., and Georgiev, V. P. |
| College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering College of Science and Engineering > School of Physics and Astronomy |
| Journal Name: | IEEE Transactions on Electron Devices |
| Publisher: | IEEE |
| ISSN: | 0018-9383 |
| ISSN (Online): | 1557-9646 |
| Published Online: | 02 April 2018 |
| Copyright Holders: | Copyright © 2018 IEEE |
| First Published: | First published in IEEE Transactions on Electron Devices 65(5): 1692-1698 |
| Publisher Policy: | Reproduced under a Creative Commons License |
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