Z²-FET as capacitor-less eDRAM cell for high-density integration

Navarro, C. et al. (2017) Z²-FET as capacitor-less eDRAM cell for high-density integration. IEEE Transactions on Electron Devices, 64(12), pp. 4904-4909. (doi: 10.1109/TED.2017.2759308)

151818.pdf - Accepted Version



2-D numerical simulations are used to demonstrate the Z²-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Asenov, Professor Asen and Duan, Dr Meng and Cheng, Dr Binjie and Adamu-Lema, Dr Fikru
Authors: Navarro, C., Duan, M., Parihar, M. S., Adamu-Lema, F., Coseman, S., Lacord, J., Lee, K., Sampedro, C., Cheng, B., El Dirani, H., Barbe, J.-C., Fonteneau, P., Kim, S.-I., Cristoloveanu, S., Bawedin, M., Millar, C., Galy, P., Le Royer, C., Karg, S., Riel, H., Wells, P., Kim, Y.-T., Asenov, A., and Gamiz, F.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Transactions on Electron Devices
ISSN (Online):1557-9646
Published Online:31 October 2017
Copyright Holders:Copyright © 2017 IEEE
First Published:First published in IEEE Transactions on Electron Devices 64(12): 4904-4909
Publisher Policy:Reproduced in accordance with the publisher copyright policy

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