Vertically Stacked Lateral Nanowire Transistors: Optimisation for 5nm CMOS Technology

Al-Ameri, T. (2017) Vertically Stacked Lateral Nanowire Transistors: Optimisation for 5nm CMOS Technology. 12th IEEE Nanotechnology Materials and Devices Conference (NMDC 2017), Singapore, 2-4 Oct 2017.

Abstract

In this work, for the first time we employ ensemble Monte Carlo /2D-Poisson-Schrödinger to study the impact of golden ratio Phi on the performance of the vertically stacked lateral silicon nanowire transistor. The design of experiment and solution for the uniformity of the current density are also discussed.

• Item Type: Conference or Workshop Item
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Al-Ameri, Talib Mahmood Ali
• Authors: Al-Ameri, T.
• College/School: College of Science and Engineering > School of Engineering
• Copyright Holders: Copyright © 2017 IEEE
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher

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