Simulations of Sub-100 nm Strained Si MOSFETs with High-k Gate Stacks

Watling, J. (2005) Simulations of Sub-100 nm Strained Si MOSFETs with High-k Gate Stacks. Computational Electronics, 3(39541), pp. 171-176.

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Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Watling, Dr Jeremy
Authors: Watling, J.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Computational Electronics

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