Al-Ameri, T. M. A. and Asenov, A. (2017) Vertically Stacked Lateral Si80Ge20 Nanowires Transistors for 5 nm CMOS Applications. In: Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2017), Athens, Greece, 3-5 Apr 2017, pp. 101-104. ISBN 9781509053131 (doi: 10.1109/ULIS.2017.7962612)
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Abstract
In this work we present a simulation study of Si80Ge20 and Silicon vertically stacked lateral nanowires transistors (NWTs) with potential application at 5nm CMOS technology node. Our simulation approach is based on careful selection of simulations techniques in order to capture the complexity of such ultra-scaled devices. We have used ensemble Monte Carlo (MC) simulations to accurately predict the drive current considering the complexity of the carrier transport in the NWTs. We have used also drift-diffusion (DD) simulations with quantum corrections based on Poisson-Schrodinger solution to accurately calibrate the density-gradient based DD quantum corrections. Finally, we have benchmarked the current in Si80Ge20 NWTs against Si based NWT.
| Item Type: | Conference Proceedings |
|---|---|
| Status: | Published |
| Refereed: | Yes |
| Glasgow Author(s) Enlighten ID: | Asenov, Professor Asen and Al-Ameri, Talib Mahmood Ali |
| Authors: | Al-Ameri, T. M. A., and Asenov, A. |
| College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering |
| ISSN: | 2472-9132 |
| ISBN: | 9781509053131 |
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