Nabi, S. W. and Vanderbauwhede, W. (2016) A Fast and Accurate Cost Model for FPGA Design Space Exploration in HPC Applications. In: 30th IEEE International Parallel & Distributed Processing Symposium, Chicago, IL, USA, 23-27 May 2016, (doi: 10.1109/IPDPSW.2016.155)
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117338.pdf - Accepted Version 1MB |
Abstract
Heterogeneous High-Performance Computing (HPC) platforms present a significant programming challenge, especially because the key users of HPC resources are scientists, not parallel programmers. We contend that compiler technology has to evolve to automatically create the best program variant by transforming a given original program. We have developed a novel methodology based on type transformations for generating correct-by-construction design variants, and an associated light-weight cost model for evaluating these variants for implementation on FPGAs. In this paper we present a key enabler of our approach, the cost model. We discuss how we are able to quickly derive accurate estimates of performance and resource-utilization from the design’s representation in our intermediate language. We show results confirming the accuracy of our cost model by testing it on three different scientific kernels. We conclude with a case-study that compares a solution generated by our framework with one from a conventional high-level synthesis tool, showing better performance and power-efficiency using our cost model based approach.
| Item Type: | Conference Proceedings |
|---|---|
| Status: | Published |
| Refereed: | Yes |
| Glasgow Author(s) Enlighten ID: | Vanderbauwhede, Professor Wim and Nabi, Dr Syed Waqar |
| Authors: | Nabi, S. W., and Vanderbauwhede, W. |
| College/School: | College of Science and Engineering > School of Computing Science |
| Copyright Holders: | Copyright © 2016 IEEE |
| Publisher Policy: | Reproduced in accordance with the copyright policy of the publisher. |
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