Heidari, H. , Navaraj, W., Toldi, G. and Dahiya, R. (2016) Device Modelling of Bendable MOS Transistors. In: IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 22-25 May 2016, pp. 1358-1361. ISBN 9781479953417 (doi: 10.1109/ISCAS.2016.7527501)
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Publisher's URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7527501&newsearch=true&queryText=Device%20Modelling%20of%20Bendable%20MOS%20Transistors
Abstract
This paper presents the directions for computer aided design, modelling and simulation of bendable MOSFET transistors towards futuristic bendable ICs. In order to compensate the bending stress a generalised geometry variation is discussed. Based on drain-current and threshold-voltage parameters varying under the bending stress, a Verilog-A compact model is proposed and describes I-V characteristics of a MOSFET in a standard 0.18-μm CMOS technology. This model has been compiled into Cadence environment to predict value and orientation of the bending stress. The proposed model validates against macro-model simulation results, and agrees for both the electron and hole conduction. It has been found that there is significant performance advantage in process-induced uniaxial stressed n-MOSFET, exhibiting a smaller drain-current variation and threshold voltage shift by monitoring the bending stress and changing the supply voltage.
Item Type: | Conference Proceedings |
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Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Dahiya, Professor Ravinder and Heidari, Professor Hadi and Navaraj, Mr William |
Authors: | Heidari, H., Navaraj, W., Toldi, G., and Dahiya, R. |
College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering |
ISBN: | 9781479953417 |
Copyright Holders: | Copyright © 2016 Institute of Electrical and Electronics Engineers |
Publisher Policy: | Reproduced in accordance with the copyright policy of the publisher |
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