Study of local power dissipation in ultrascaled silicon nanowire FETs

Martinez, A., Barker, J. R., Aldegunde, M. and Valin, R. (2015) Study of local power dissipation in ultrascaled silicon nanowire FETs. IEEE Electron Device Letters, 36(1), pp. 2-4. (doi: 10.1109/LED.2014.2368357)

Abstract

The local electron power dissipation has been calculated in a field-effect nanowire transistor using a quantum transport formalism. Two different channel cross sections and optical and acoustic phonon mechanisms were considered. The phonon models used reproduce the phonon limited mobility in the cross sections studied. The power dissipation for different combinations of source, channel, and drain dimensions have been calculated. Due to the lack of complete electron energy relaxation inside the device, the Joule heat dissipation over-estimates the power dissipated in small nanotransistors. This over-estimation is larger for large cross sections due to the weaker phonon scattering. On the other hand, in narrow wires, the power dissipation inside the device can be large, therefore, mitigating against fabrication of very narrow nanowire transistors. We have also investigated the cooling of the device source region due to the mismatch of the Peltier coefficients between the source and the channel.

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Barker, Professor John and Martinez, Dr Antonio
• Authors: Martinez, A., Barker, J. R., Aldegunde, M., and Valin, R.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: IEEE Electron Device Letters
• Publisher: IEEE
• ISSN: 0741-3106
• ISSN (Online): 1558-0563
• Copyright Holders: Copyright © 2014 The Authors
• First Published: First published in IEEE Electron Device Letters 36(1):2-4
• Publisher Policy: Reproduced under a Creative Commons License