Browse by Research Project Code

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0

Medina Bailon, C., Sadi, T., Nedjalkov, M., Carrillo Nenez, C., Lee, J., Badami, O., Georgiev, V. , Selberherr, S. and Asenov, A. (2019) Mobility of circular and elliptical si nanowire transistors using a multi-subband 1d formalism. IEEE Electron Device Letters, (doi:10.1109/LED.2019.2934349) (Early Online Publication)

Sadi, T., Medina Bailon, C., Nedjalkov, M., Lee, J., Badami, O., Berrada, S., Carrillo-Nunez, H., Georgiev, V. , Selberherr, S. and Asenov, A. (2019) Simulation of the impact of ionized impurity scattering on the total mobility in Si nanowire transistors. Materials, 12(1), 124. (doi:10.3390/ma12010124)

Lee, J., Medina-Bailon, C., Berrada, S., Carrillo-Nunez, H., Sadi, T., Georgiev, V. P. , Nedjalkov, M. and Asenov, A. (2019) A Multi-Scale Simulation Study of the Strained Si Nanowire FETs. In: 2018 IEEE 13th Nanotechnology Materials & Devices Conference (NMDC 2018), Portland, OR, USA, 14-17 Oct 2018, ISBN 9781538610169 (doi:10.1109/NMDC.2018.8605884)

Medina Bailon, C., Sadi, T., Sampedro, C., Padilla, J. L., Donetti, L., Georgiev, V. , Gamiz, F. and Asenov, A. (2019) Impact of the trap attributes on the gate leakage mechanisms in a 2D MS-EMC nanodevice simulator. In: Nikolov, G., Kolkovska, N. and Georgiev, K. (eds.) Numerical Methods and Applications. Series: Lecture Notes in Computer Science, 11189 (11189). Springer, pp. 273-280. ISBN 9783030106911 (doi:10.1007/978-3-030-10692-8_30)

Lee, J., Badami, O., Carrillo-Nunez, H., Berrada, S., Medina-Bailon, C., Dutta, T., Adamu-Lema, F., Georgiev, V. P. and Asenov, A. (2018) Variability predictions for the next technology generations of n-type SixGe1-x nanowire MOSFETs. Micromachines, 9(12), 643. (doi:10.3390/mi9120643)

Berrada, S., Lee, J., Carrillo-Nunez, H., Medina Bailon, C., Adamu-Lema, F., Georgiev, V. and Asenov, A. (2018) Quantum Transport Investigation of Threshold Voltage Variability in Sub-10 nm JunctionlessSi Nanowire FETs. In: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Austin, TX, 24-26 Sept 2018, pp. 244-247. ISBN 9781538667910 (doi:10.1109/SISPAD.2018.8551638)

Medina Bailon, C., Sadi, T., Nedjalkov, M., Lee, J., Berrada, S., Carrillo-Nunez, H., Georgiev, V. P. , Selberherr, S. and Asenov, A. (2018) Impact of the Effective Mass on the Mobility in Si Nanowire Transistors. In: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Austin, TX, 24-26 Sept 2018, pp. 297-300. ISBN 9781538667910 (doi:10.1109/SISPAD.2018.8551630)

Nedjalkov, M., Ellinghaus, P., Weinbub, J., Sadi, T., Asenov, A., Dimov, I. and Selberherr, S. (2018) Stochastic analysis of surface roughness models in quantum wires. Computer Physics Communications, 228, pp. 30-37. (doi:10.1016/j.cpc.2018.03.010)

Medina Bailon, C., Sadi, T., Nedjalkov, M., Lee, J., Berrada, S., Carrillo-Nunez, H., Georgiev, V. , Selberherr, S. and Asenov, A. (2018) Study of the 1D Scattering Mechanisms' Impact on the Mobility in Si Nanowire Transistors. In: 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Granada, Spain, 19-21 Mar 2018, ISBN 9781538648117 (doi:10.1109/ULIS.2018.8354723)

Al-Ameri, T. (2018) Correlation between the golden ratio and nanowire transistor performance. Applied Sciences, 8(1), 54. (doi:10.3390/app8010054)

Al-Ameri, T. , Georgiev, V.P. , Adamu-Lema, F. and Asenov, A. (2017) Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications. IEEE Journal of the Electron Devices Society, 5(6), pp. 466-472. (doi:10.1109/JEDS.2017.2752465)

Georgiev, V. P. , Mirza, M. M. , Dochioiu, A.-I., Lema, F.-A., Amoroso, S. M., Towie, E., Riddet, C., MacLaren, D. A. , Asenov, A. and Paul, D. J. (2017) Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels. IEEE Transactions on Nanotechnology, 16(5), pp. 727-735. (doi:10.1109/TNANO.2017.2665691)

Al-Ameri, T. M. A. and Asenov, A. (2017) Vertically Stacked Lateral Si80Ge20 Nanowires Transistors for 5 nm CMOS Applications. In: Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2017), Athens, Greece, 3-5 Apr 2017, pp. 101-104. ISBN 9781509053131 (doi:10.1109/ULIS.2017.7962612)

Georgiev, V. P. , Mirza, M. M. , Dochioiu, A.-I., Lema, F.-A., Amoroso, S. M., Towie, E., Riddet, C., MacLaren, D. A. , Asenov, A. and Paul, D. J. (2016) Experimental and Simulation Study of a High Current 1D Silicon Nanowire Transistor Using Heavily Doped Channels. In: 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), Toulouse, France, 9-12 Oct 2016, ISBN 9781509043521 (doi:10.1109/NMDC.2016.7777084)

Sadi, T., Towie, E., Nedjalkov, M., Riddet, C., Alexander, C., Wang, L., Georgiev, V. , Brown, A., Millar, C. and Asenov, A. (2016) One-Dimensional Multi-Subband Monte Carlo Simulation of Charge Transport in Si Nanowire Transistors. In: SISPAD 2016: International Conference on Simulation of Semiconductor Processes and Devices, Nuremberg, Germany, 6-8 Sept 2016, pp. 23-26. ISBN 9781509008186 (doi:10.1109/SISPAD.2016.7605139)

Al-Ameri, T. , Georgiev, V. P. , Lema, F.-A., Sadi, T., Wang, X., Towie, E., Riddet, C., Alexander, C. and Asenov, A. (2016) Impact of Strain on the Performance of Si Nanowires Transistors at the Scaling Limit: A 3D Monte Carlo/2D Poisson Schrodinger Simulation Study. In: SISPAD 2016: International Conference on Simulation of Semiconductor Processes and Devices, Nuremberg, Germany, 6-8 Sept 2016, pp. 213-216. ISBN 9781509008186 (doi:10.1109/SISPAD.2016.7605185)

This list was generated on Fri Dec 13 04:01:08 2019 GMT.