The Glasgow Parallel Reduction Machine: programming shared-memory many-core systems using parallel task composition

Tousimojarad, A. and Vanderbauwhede, W. (2013) The Glasgow Parallel Reduction Machine: programming shared-memory many-core systems using parallel task composition. Electronic Proceedings in Theoretical Computer Science, 137, pp. 79-94. (doi:10.4204/EPTCS.137.7)

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Abstract

We present the Glasgow Parallel Reduction Machine (GPRM), a novel, flexible framework for parallel task-composition based many-core programming. We allow the programmer to structure programs into task code, written as C++ classes, and communication code, written in a restricted subset of C++ with functional semantics and parallel evaluation. In this paper we discuss the GPRM, the virtual machine framework that enables the parallel task composition approach. We focus the discussion on GPIR, the functional language used as the intermediate representation of the bytecode running on the GPRM. Using examples in this language we show the flexibility and power of our task composition framework. We demonstrate the potential using an implementation of a merge sort algorithm on a 64-core Tilera processor, as well as on a conventional Intel quad-core processor and an AMD 48-core processor system. We also compare our framework with OpenMP tasks in a parallel pointer chasing algorithm running on the Tilera processor. Our results show that the GPRM programs outperform the corresponding OpenMP codes on all test platforms, and can greatly facilitate writing of parallel programs, in particular non-data parallel algorithms such as reductions.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Professor Wim and Tousimojarad, Dr Ashkan
Authors: Tousimojarad, A., and Vanderbauwhede, W.
College/School:College of Science and Engineering > School of Computing Science
Journal Name:Electronic Proceedings in Theoretical Computer Science
Publisher:Open Publishing Association
ISSN:2075-2180
Copyright Holders:Copyright © 2013 The Authors
First Published:First published in Electronic Proceedings in Theoretical Computer Science 137:79-94
Publisher Policy:Reproduced under a Creative Commons License

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
389341A novel service-based system on a chip architecture using on chip networks with smart packets and dynamically reconfigurable logicWim VanderbauwhedeEngineering & Physical Sciences Research Council (EPSRC)GR/T03239/01COM - COMPUTING SCIENCE