SRAM device and cell co-design considerations in a 14nm SOI FinFET technology

Cheng, B., Wang, X., Brown, A.R., Kuang, J.B., Reid, D., Millar, C., Nassif, S. and Asenov, A. (2013) SRAM device and cell co-design considerations in a 14nm SOI FinFET technology. In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May 2013, pp. 2339-2342. (doi: 10.1109/ISCAS.2013.6572347)

Abstract

We report a systematic study on the impact of process and statistical variability on SRAM design in a 14nm SOI FinFET technology node. A comprehensive statistical compact modelling strategy is developed for the early delivery of reliable PDK model, which enables TCAD-based transistor-cell co-design and path finding during the early phase of a technology node.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Millar, Dr Campbell and Reid, Mr David and Brown, Mr Andrew and Cheng, Dr Binjie and Wang, Dr Xingsheng and Asenov, Professor Asen
• Authors: Cheng, B., Wang, X., Brown, A.R., Kuang, J.B., Reid, D., Millar, C., Nassif, S., and Asenov, A.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering