III-V MOSFET Fabrication and Device (Fabrication process of e.g. group III-V MOSFET for nano complementary metal oxide semiconductor application, involves heat treating metal contact structure to produce alloy region within semiconductor substrate)

Freescale Semiconductor, Inc. (2009) III-V MOSFET Fabrication and Device (Fabrication process of e.g. group III-V MOSFET for nano complementary metal oxide semiconductor application, involves heat treating metal contact structure to produce alloy region within semiconductor substrate). .

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Publisher's URL: http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1=20090189252.PGNR.

Abstract

A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45.degree. to 90.degree.. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

Item Type:Patents
Additional Information:Publication number: US 20090189252 A1; US7842587-B2. Application number: US 12/022,942.
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Li, Dr Xu and Zhou, Dr Haiping and Thayne, Professor Iain and Hill, Mr Richard and Moran, Dr David
Authors: Abrokwah, J.K., Hill, R.H., Li, X., Moran, D.A., Passlack, M., Rajagopalan, K., Thayne, I.G., Zhou, H., and Zurcher, P.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

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