A simple silicon compatible 40nm electroplated copper T-gate process

Cao, M., Li, X. , Ferguson, S., Thoms, S. , Macintyre, D. and Thayne, I. (2014) A simple silicon compatible 40nm electroplated copper T-gate process. Microelectronic Engineering, 121, pp. 153-155. (doi: 10.1016/j.mee.2014.05.007)

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Publisher's URL: http://dx.doi.org/10.1016/j.mee.2014.05.007


This paper reports a simple route to fabricating T-gate like structures with footprint of 40 nm using a copper electroplating process and a single electron beam lithography step without the need for lift-off. To our knowledge, these are the smallest such structures demonstrated using this approach which could also be implemented straightforwardly using conventional stepper or nanoimprint lithography for low cost, high volume silicon compatible manufacture.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Thayne, Prof Iain and Thoms, Dr Stephen and Ferguson, Mrs Susan and Li, Dr Xu and Macintyre, Dr Douglas
Authors: Cao, M., Li, X., Ferguson, S., Thoms, S., Macintyre, D., and Thayne, I.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Microelectronic Engineering
ISSN (Online):1873-5568

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